Fast and accurate parasitic capacitance models for layout-aware

Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow. A layout aware methodology for synthesis of analog CMOS circuits using these parasitic models is presented. Results indicate that the proposed synthesis system is fast as compared to a layout-inclusive synthesis approach. Categories and Subject Descriptors B.7.2 [Hardware]: Design Aids General Terms Algorithms Keywords Analog Synthesis, Layout Aware, Parasitic Estimation

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
• Keywords: Computer Architecture, DAC 2004, Keywords Analog Synthesis, Parasitic, Parasitic Capacitances