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DAC
2004
ACM

Fast and accurate parasitic capacitance models for layout-aware

10 years 3 months ago
Fast and accurate parasitic capacitance models for layout-aware
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow. A layout aware methodology for synthesis of analog CMOS circuits using these parasitic models is presented. Results indicate that the proposed synthesis system is fast as compared to a layout-inclusive synthesis approach. Categories and Subject Descriptors B.7.2 [Hardware]: Design Aids General Terms Algorithms Keywords Analog Synthesis, Layout Aware, Parasitic Estimation
Anuradha Agarwal, Hemanth Sampath, Veena Yelamanch
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where DAC
Authors Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
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