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2002
IEEE

Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems

9 years 3 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where FCCM
Authors Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi
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