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ISCAS
2006
IEEE

Fast bit permutation unit for media enhanced microprocessors

9 years 12 months ago
Fast bit permutation unit for media enhanced microprocessors
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-purpose microprocessors to efficiently implement the required data permutations. In this paper, the design of a high speed bit permutation unit is examined. The proposed architecture has been derived by mapping the functionality of one of the most powerful bit permutation instructions (GRP) to a new enhanced bitonic sorting network. The proposed design achieves delay reductions more than 20% when compared with previously presented solutions, while its regularity enables efficient VLSI implementations.
Giorgos Dimitrakopoulos, Christos Mavrokefalidis,
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where ISCAS
Authors Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
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