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FPL
2009
Springer

Fast critical sections via thread scheduling for FPGA-based multithreaded processors

12 years 19 days ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these systems. Previous work has demonstrated that support for multithreading in soft processors can tolerate pipeline and I/O latencies as well as improve overall system throughput—however earlier work assumes an abundance of completely independent threads to execute. In this work we show that for real workloads, in particular packet processing applications, there is a large fraction of processor cycles wasted while awaiting the synchronization of shared data structures, limiting the benefits of a multithreaded design. We address this challenge by proposing a method of scheduling threads in hardware that allows the multithreaded pipeline to be more fully utilized without significant costs in area or frequency. We evaluate our technique relative to conventional multithreading using both simulation and a real i...
Martin Labrecque, J. Gregory Steffan
Added 24 Jul 2010
Updated 24 Jul 2010
Type Conference
Year 2009
Where FPL
Authors Martin Labrecque, J. Gregory Steffan
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