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ASPDAC
2004
ACM

Fast, predictable and low energy memory references through architecture-aware compilation

11 years 10 months ago
Fast, predictable and low energy memory references through architecture-aware compilation
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, current cache-based approaches for bridging the increasing speed gap between processors and memories cannot guarantee predictable real-time behavior. A contribution to solving both problems is made in this paper which describes a comprehensive set of algorithms that can be applied at design time in order to maximally exploit scratch pad memories (SPMs). We show that both the energy consumption as well as the computed worst case execution time (WCET) can be reduced by up to to 80% and 48%, respectively, by establishing a strong link between the memory architecture and the compiler.
Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefa
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where ASPDAC
Authors Peter Marwedel, Lars Wehmeyer, Manish Verma, Stefan Steinke, Urs Helmig
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