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Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations

9 years 1 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined with simulation based-techniques used for constraints solving. The gate-level local test patterns for components are randomly generated driven by highlevel constraints and partial path activation solutions. Experiments show that high fault coverages for circuits with complex sequential structures can be achieved in a very short time by using this approach.
Jaan Raik, Raimund Ubar
Added 18 Dec 2010
Updated 18 Dec 2010
Type Journal
Year 2000
Where ET
Authors Jaan Raik, Raimund Ubar
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