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ITC
2002
IEEE

Fault Grading FPGA Interconnect Test Configurations

13 years 8 months ago
Fault Grading FPGA Interconnect Test Configurations
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. Compared to conventional methods, our technique is orders of magnitude faster, while is able to report all detectable and undetectable faults.
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin T
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where ITC
Authors Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
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