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14

IOLTS
2006
IEEE

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Fault Tolerant System Design Method Based on Self-Checking Circuits

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Fault Tolerant System Design Method Based on Self-Checking Circuits

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This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.

Pavel Kubalík, Petr Fiser, Hana Kubatova

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IOLTS 2006 | Parity Groups | Parity Predictor | Self Checking Blocks | Software Engineering |

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Added	11 Jun 2010
Updated	11 Jun 2010
Type	Conference
Year	2006
Where	IOLTS
Authors	Pavel Kubalík, Petr Fiser, Hana Kubatova

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