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DAC
2007
ACM

Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

10 years 9 months ago
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in Distributed Sleep Transistor Network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids General Terms Performance, Design Keywords Leakage Current, Power Gating, IR Drop
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2007
Where DAC
Authors De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang
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