Flexible instruction processors

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Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our approach include: (a) a modular framework based on "processor templates" that capture various instruction processor styles, such as stack-based or register-based styles; (b) enhancements of this framework to improve functionality and performance, such as hybrid processor templates and superscalar operation; (c) compilation strategies involving standard compilers and FIP-specific compilers, and the associated design flow; (d) technology-independent and technology-specific optimisations, such as techniques for efficient resource sharing in FPGA implementations. Our current implementation of the FIP framework is based on a highlevel parallel language called Handel-C, which can be compiled into hardware. Various customised Java Virtual Machines and MIPS style processors have been developed using existing F...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Authors Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
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