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2002
IEEE

Flip-Flop and Repeater Insertion for Early Interconnect Planning

10 years 1 months ago
Flip-Flop and Repeater Insertion for Early Interconnect Planning
We present a unified framework that considers flipflop and repeater insertion and the placement of flipflop/repeater blocks during RT or higher level design. We introduce the concept of independent feasible regions in which flip-flops and repeaters can be inserted in an interconnect to satisfy both delay and cycle time constraints. Experimental results show that, with flip-flop insertion, we greatly increase the ability of interconnects to meet timing constraints. Our results also show that it is necessary to perform interconnect optimization at early design steps as the optimization will have even greater impact on the chip layout as feature size continually scales down.
Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan C
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where DATE
Authors Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
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