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2003
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Floating Point Unit Generation and Evaluation for FPGAs

9 years 3 months ago
Floating Point Unit Generation and Evaluation for FPGAs
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floating point units with differing throughput, latency, and area characteristics. Given performance requirements, our generation tool automatically chooses the proper implementation algorithm and architecture to create a compliant floating point unit. Our approach is fully integrated into standard C++ using ASC, a stream compiler for FPGAs, and the PAM-Blox II module generation environment. The floating point units created by our approach exhibit a factor of two latency improvement versus commercial FPGA floating point units, while consuming only half of the FPGA logic area.
Jian Liang, Russell Tessier, Oskar Mencer
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where FCCM
Authors Jian Liang, Russell Tessier, Oskar Mencer
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