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ISQED
2002
IEEE

Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning

12 years 29 days ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout optimization. As the SIA technology roadmap predicts, however, the number of interconnections among different blocks and that of buffers inserted in a chip for performance optimization will grow dramatically [17, 18]. It is obviously infeasible to insert/size hundreds of thousands buffers or wires during the post-layout stage when most routing regions are occupied. Therefore, it is critical to incorporate buffer-block and wire-size planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive continuous buffer insertion/sizing and wire sizing formulae for performance optimization under a more accurate wire model, and then apply the formulae to inte...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where ISQED
Authors Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang
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