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An FPGA architecture for CABAC decoding in manycore systems

8 years 5 months ago
An FPGA architecture for CABAC decoding in manycore systems
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arithmetic decoding (AD) in H.264 video coding standard is a sequential task that takes a significant part of computing time. In present and future multicore and manycore systems, AD becomes a bottleneck as it cannot be parallelized, limiting the concurrent execution of other tasks. In this paper, an FPGA-based accelerator is proposed to speed-up AD in H.264 and enable parallel decoding at macroblock and frame levels scaling up to tens or hundreds of cores.
Roberto R. Osorio, Javier D. Bruguera
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where ASAP
Authors Roberto R. Osorio, Javier D. Bruguera
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