An FPGA-based high-speed, low-latency trigger processor for high-energy physics

An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 TBit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules and one top module. All modules contain the same FPGA, DDR SRAM and SDRAM, but are equipped with different optional components and additional interface boards, which simplifies significantly the hardware development and reduces the costs. The first successful test of the system in real environment was performed in December 2007. Further FPGA design improvements like Linux OS for the embedded PowerPC processors and extended diagnostics and control using Ethernet are under development.

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth
• Keywords: FPGA Based Application, FPGA Design, FPL 2008, Hardware, Modern Fpga Design