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2011
Springer

FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

7 years 11 months ago
FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control
Abstract. The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effect...
Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Dev
Added 13 Dec 2011
Updated 13 Dec 2011
Type Journal
Year 2011
Where CHES
Authors Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Devadas
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