Sciweavers

Share
ITNG
2007
IEEE

FPGA-based Vector Processing for Matrix Operations

9 years 11 months ago
FPGA-based Vector Processing for Matrix Operations
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor is implemented on the Xilinx XC2V6000-5 FPGA chip. To test the performance, the W-matrix sparse solver for linear equations is realized. W-matrix was first proposed for power flow analysis and is prone to parallel computing. We show that actual power matrices with up to 1723 nodes can be dealt with in less
Hongyan Yang, Sotirios G. Ziavras, Jie Hu
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ITNG
Authors Hongyan Yang, Sotirios G. Ziavras, Jie Hu
Comments (0)
books