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2010

FPGA Designs with Optimized Logarithmic Arithmetic

8 years 10 months ago
FPGA Designs with Optimized Logarithmic Arithmetic
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate comparison between LNS and floating-point designs.
Haohuan Fu, Oskar Mencer, Wayne Luk
Added 21 May 2011
Updated 21 May 2011
Type Journal
Year 2010
Where TC
Authors Haohuan Fu, Oskar Mencer, Wayne Luk
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