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2008
IEEE

FPGA Implementation of an Adaptive Noise Canceller

8 years 8 months ago
FPGA Implementation of an Adaptive Noise Canceller
This paper proposes an FPGA implementation of an Adaptive Noise Canceller using the Least Mean Square (LMS) algorithm. The hardware architecture is synthesized using the Xilinx Spartan-3e Starter Kit as the target board. The experimental result of the hardware implementation shows the performance of LMS algorithm under different conditions and the feasibility of our architecture. A comparison between hardware and pure software implementation is then made with different filter taps.
Tian Lan, Jinlin Zhang
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISIP
Authors Tian Lan, Jinlin Zhang
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