An FPGA Implementation of Dirty Paper Precoder

—Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We study various implementation bottlenecks and issues with implementing a DPC pre-coder based on nested trellis technique. The aim is to achieve a practical hardware realization of the precoder for wireless LAN/DSL applications. We describe the architectural development process and realization of the precoder on a Xilinx Virtex 2V8000 FPGA. To the best of our knowledge this is the first reported DPC pre-coder hardware implementation.

• Type: Conference
• Year: 2007
• Where: ICC
• Authors: Pankaj Bhagawat, Weihuang Wang, Momin Uppal, Gwan Choi, Zixiang Xiong, Mark B. Yeary, Alan Harris
• Keywords: Communications, DPC Pre-coder, DPC Pre-coder Hardware, ICC 2007, Multiuser Interference Channels