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FPL
2003
Springer

FPGA Implementation of a Maze Routing Accelerator

13 years 8 months ago
FPGA Implementation of a Maze Routing Accelerator
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction.
John A. Nestor
Added 06 Jul 2010
Updated 06 Jul 2010
Type Conference
Year 2003
Where FPL
Authors John A. Nestor
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