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DELTA
2008
IEEE

FPGA implementation of a Single Pass Connected Components Algorithm

10 years 6 months ago
FPGA implementation of a Single Pass Connected Components Algorithm
The classic connected components labelling algorithm requires two passes through an image. This paper presents an algorithm that allows the connected components to be analysed in a single pass by gathering data on the regions as they are built. This avoids the need for buffering the image, making it ideally suited for processing streamed images on an FPGA or other embedded system with limited memory. An FPGA-based implementation is described, emphasising the modifications made to the algorithm to enable it to satisfy timing constraints.
Christopher T. Johnston, Donald G. Bailey
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DELTA
Authors Christopher T. Johnston, Donald G. Bailey
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