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2003
IEEE

FPGA Interconnect Delay Fault Testing

10 years 7 months ago
FPGA Interconnect Delay Fault Testing
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple interconnect delay faults, multiple bridging faults, or both. An adjustable maximum sensitivity to resistive open defects of several kilo-ohms is achieved. A bridging fault that causes a signal transition to occur on at least one of the bridged interconnects is detectable. Finally, fast and simple fault location is presented.
Erik Chmelar
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ITC
Authors Erik Chmelar
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