Sciweavers

Share
SEUS
2007
IEEE

A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture

12 years 2 months ago
A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as recently developed in DECOS (Dependable Embedded COmponents and Systems), an integrated project within the Sixth Framework Programme of the European Commission. Focusing on the interconnection between the simulated environment and the Integrated System Under Test (ISUT), our approach involves the concept of a Smart Virtual Transducer (SVT) that replaces the physical transducers of the ISUT without a probe effect on the ISUT. Our approach enables a complexity reduction for setting up an HiL simulation and supports a well-designed scalable interface to an integrated architecture. Furthermore, we support non-intrusive, deterministic interaction between the environment simulation system and the ISUT in order to guarantee reproducible test-runs. We show an exemplary application of the proposed concept by tailoring t...
Martin Schlager, Roman Obermaisser, Wilfried Elmen
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where SEUS
Authors Martin Schlager, Roman Obermaisser, Wilfried Elmenreich
Comments (0)
books