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DAC
2007
ACM

A Framework for the Validation of Processor Architecture Compliance

13 years 8 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing behavior, wrong understanding of a behavior, or confusion with similar behavior described in the architecture or elsewhere. We formally capture the architecture behavior in the form of flowcharts and automatically derive a list of architecture misinterpretations from these flowcharts. These misinterpretations constitute the backbone of coverage models targeted by a suite of tests. The suite is automatically generated by a model-based test case generator. A compliance validation system based on these principles has been developed and used in two actual industrial processes of checking compliance with the PowerPC architecture. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids--Verification General Terms Verification, Experimentation, Standardization Keywords Compliance suite, Conformance, Proce...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae
Added 14 Aug 2010
Updated 14 Aug 2010
Type Conference
Year 2007
Where DAC
Authors Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled
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