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IEEEIAS
2009
IEEE

Full System Simulation and Verification Framework

10 years 11 months ago
Full System Simulation and Verification Framework
In this paper, we propose a framework to develop highperformance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chu
Added 19 Feb 2011
Updated 19 Feb 2011
Type Journal
Year 2009
Where IEEEIAS
Authors Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
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