Future Performance Challenges in Nanometer Design

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Future Performance Challenges in Nanometer Design
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power scaling trends lead to major packaging problems. To alleviate these concerns, thermal monitoring and feedback mechanisms can limit worst-case dissipation and reduce costs. Furthermore, a flexible multi-Vdd + multi-Vth + re-sizing approach is advocated to leverage the inherent properties of ultrasmall MOSFETs and limit both dynamic and static power. Alternative global signaling strategies such as differential and low-swing drivers are recommended in order to curb the power requirements of crosschip communication. Finally, potential power delivery challenges are addressed with respect to ITRS packaging predictions.
Dennis Sylvester, Himanshu Kaul
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2001
Where DAC
Authors Dennis Sylvester, Himanshu Kaul
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