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7

DATE
1998
IEEE

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Gated Clock Routing Minimizing the Switched Capacitance

13 years 8 months ago

Gated Clock Routing Minimizing the Switched Capacitance

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This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce switched capacitance of the clock tree. This work extends the work of [4] so as to account for the switched capacitance and the area of the gate control signal routing. Various tradeoffs between power and area for different design options and module activities are discussed and detailed experimental results are presented

Jaewon Oh, Massoud Pedram

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Clock Tree | DATE 1998 | Gate Control Signal | Gated Clock | Hardware |

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Added	04 Aug 2010
Updated	04 Aug 2010
Type	Conference
Year	1998
Where	DATE
Authors	Jaewon Oh, Massoud Pedram

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