A generalized methodology for lower-error area-efficient fixed-width multipliers

In this paper, we extend our generalized methodology for designing lower-error area-efficient fixed-width two’s-complement multipliers that receive two s -bit numbers and produce an s -bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to lower-error fixed-width multipliers suitable for VLSI realization.

• Type: Conference
• Year: 2002
• Where: ISCAS
• Authors: Lan-Da Van, Sung-Huang Lee
• Keywords: Better Error-compensation Biases, Fixed-width Two’s-complement Multipliers, Generalized Methodology, Hardware, ISCAS 2002