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ENTCS
2010

Geometry of Synthesis II: From Games to Delay-Insensitive Circuits

13 years 3 months ago
Geometry of Synthesis II: From Games to Delay-Insensitive Circuits
This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [4]. We introduce concurrency, an essential feature in the context of hardware compilation and we re-use an existing game model to simplify correctness proofs. The target designs we compile to are asynchronous event-logic circuits, which naturally match the asynchronous game model of the language.
Dan R. Ghica, Alex Smith
Added 10 Dec 2010
Updated 10 Dec 2010
Type Journal
Year 2010
Where ENTCS
Authors Dan R. Ghica, Alex Smith
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