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2008

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

8 years 5 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay elements to the logic blocks of the FPGA. After routing a circuit and performing static timing analysis, these delay elements are programmed to align the arrival times of the inputs of each LUT, thereby preventing new glitches from being generated. Moreover, the delay elements also behave as filters that eliminate other glitches generated by upstream logic or off-chip circuitry. On average, the proposed implementation eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires little or no modifications to the routing architecture or CAD flow.
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where TVLSI
Authors Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
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