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2000
IEEE

Global Register Partitioning

9 years 8 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large amounts of ILP hardware and aggressive instruction scheduling techniques put great demands on a machine’s register resources. With increasing ILP, it becomes difficult to maintain a single monolithic register bank and a high clock rate. To provide support for large amounts of ILP while retaining a high clock rate, registers can be partitioned among several different register banks. Each bank is directly accessible by only a subset of the functional units with explicit inter-bank copies required to move data between banks. Therefore, a compiler must deal not only with achieving maximal parallelism via aggressive scheduling, but also with data placement to limit inter-bank copies. Our approach to code generation for ILP architectures with partitioned register resources provides flexibility by representing ...
Jason Hiser, Steve Carr, Philip H. Sweany
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where IEEEPACT
Authors Jason Hiser, Steve Carr, Philip H. Sweany
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