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2007

A Graph-based Framework for High-level Test Synthesis

9 years 11 months ago
A Graph-based Framework for High-level Test Synthesis
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniques have changed their way from traditional DFT to modern SFT approach. In this paper, we present a novel flexible register allocation method for digital circuits, which is based on considering testability parameters as weights of register compatibility graph and weighted graph maximum clique algorithm in which during the synthesis, testability considerations impact on register allocation. Keywords BIST, Synthesis, Testability, Register allocation, (C)BILBO.
Ali Pourghaffari bashari, Saadat Pourmozafari
Added 07 Nov 2010
Updated 07 Nov 2010
Type Conference
Year 2007
Where WCE
Authors Ali Pourghaffari bashari, Saadat Pourmozafari
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