Hardware acceleration of multi-view face detection

—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotated image windows and their integral image windows for each classifier which perform parallel classification operations to detect non-upright (rotated) and non-frontal (profile) faces in the images. We use the training data from OpenCV to detect the frontal and profile faces based on the Viola and Jones algorithm. The proposed architecture for multi-view face detection has been designed using Verilog HDL and implemented in a Xilinx Virtex5 FPGA. Its performance has been measured and compared with a Jones' and Viola's software implementation of multi-view face detection. Keywords- acceleration, classifier, face detection, FPGA, multiview face, Verilog HDL

• Type: Conference
• Year: 2009
• Where: SASP
• Authors: Junguk Cho, Bridget Benson, Ryan Kastner
• Keywords: Hardware, Image Windows, Multi-view Face Detection, SASP 2009, Verilog HDL