A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard

We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standard. EBCOT Tier-1 accounts for more than 70% of encoding time due to extensive bit-level processing. Our architecture consists of a 16-bit parallel context formation module and a 3-stage pipelined arithmetic encoder. Compared with the known best design, we reduce 17% of the cycle count and have achieved within 5% of the theoretical lower bound. We have integrated our synthesizable RTL with an AMBA-AHB interface for SOC design. FPGA prototyping has been successfully demonstrated and substantial speedup achieved. Keywords JPEG2000, Embedded Block Coding with Optimal Truncation, Context Formation, Arithmetic Encoder.

• Type: Conference
• Year: 2004
• Where: ESTIMEDIA
• Authors: Tien-Wei Hsieh, Youn-Long Lin
• Keywords: Arithmetic Encoder, Embedded Block, ESTIMEDIA 2004, Optimal Truncation