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2002
IEEE

Hardware support for real-time embedded multiprocessor system-on-a-chip memory management

9 years 4 months ago
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
The aggressive evolution of the semiconductor industry — smaller process geometries, higher densities, and greater chip complexity — has provided design engineers the means to create complex, high-performance Systems-on-a-Chip (SoC) designs. Such SoC designs typically have more than one processor and huge memory, all on the same chip. Dealing with the global onchip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for the upcoming billion transistor multiprocessor SoC designs. To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management. To implement this memory management scheme — which presents a paradigm shift in the way designers look at on-chip dynamic memory allocation — we present a System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to...
Mohamed Shalan, Vincent John Mooney III
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where CODES
Authors Mohamed Shalan, Vincent John Mooney III
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