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1998

Hardware synthesis from protocol specifications in LOTOS

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Hardware synthesis from protocol specifications in LOTOS
: In this paper, we propose a technique for hardware implementation of protocol specifications in LOTOS. For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets, and propose a conversion algorithm from a subset of LOTOS. The derived synchronous EFSMs can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock. By applying our technique to the Abracadabra protocol, it is confirmed that the derived circuit handles multi-rendezvous efficiently.
Keiichi Yasumoto, Akira Kitajima, Teruo Higashino,
Added 01 Nov 2010
Updated 01 Nov 2010
Type Conference
Year 1998
Where FORTE
Authors Keiichi Yasumoto, Akira Kitajima, Teruo Higashino, Kenichi Taniguchi
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