Hardware/software 2D-3D backprojection on a SoPC platform

The reduction of image reconstruction time is needed to spread the use of PET for research and routine clinical practice. In this purpose, this article presents a hardware/software architecture for the acceleration of 3D backprojection based upon an efficient 2D backprojection. This architecture has been designed in order to provide a high level of parallelism thanks to an efficient management of the memory accesses which would have been otherwise strongly slowed by the external memory. The reconstruction system is embedded in a SoPC platform (System on Programmable Chip), the new generation of reconfigurable circuit. The originality of this architecture comes from the design of a 2D Adaptative and Predictive Cache (2D-AP Cache) which has proved to be an efficient way to overcome the memory access bottleneck. Thanks to a hierarchical use of this cache, several backprojection operators can run in parallel, accelerating in this manner noteworthy the reconstruction process. This 2D reco...

• Type: Conference
• Year: 2006
• Where: SAC
• Authors: Nicolas Gac, Stéphane Mancini, Michel Desvignes
• Keywords: Applied Computing, Efficient 2D Backprojection, Image Reconstruction, Image Reconstruction Time, SAC 2006