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FPL
2007
Springer

Hardware/Software Process Migration and RTL Simulation

13 years 9 months ago
Hardware/Software Process Migration and RTL Simulation
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs). The feasibility of such a system is demonstrated using existing FPGAs by accelerating a cyclebased simulation of a Register Transfer Level (RTL) design description. Through the use of a common instruction set, each simulation process may be run in a software Virtual Machine (VM) or in a hardware Real Machine (RM). The implementation provides data for an empirical model used to examine the behavior of unimplemented parts of the system.
Aric D. Blumer, Cameron D. Patterson
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where FPL
Authors Aric D. Blumer, Cameron D. Patterson
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