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1998
IEEE

HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation

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HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-speci c embedded processors. In order to achieve user retargetability, powerful processor modeling formalisms are required. Most of the recent modeling formalisms concentrate on horizontal, VLIWlike instruction formats. However, for encoded instruction formatswith restricted instruction-level parallelism ILP, a large number of ILP constraints might need to be speci ed, resulting in less concise processor models. This paper presents an HDL-based approach to processor modeling for retargetable compilation, in which ILP may be implicitly constrained. As a consequence, the formalism allows for concise models also for encoded instruction formats. The practical applicability of the modeling formalismis demonstrated by means of a case study for a complex DSP1
Rainer Leupers
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ISSS
Authors Rainer Leupers
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