HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic

Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instruction windows increase power consumption and latency in the issue logic. We propose a design called Hybrid Dataflow Graph Execution (HeDGE) for conventional Instruction Set Architectures (ISAs). HeDGE explicitly maintains dependences between instructions in the issue window by modifying the issue, register renaming, and wakeup logic. The HeDGE wakeup logic notifies only consumer instructions when data values arrive. Explicit consumer encoding naturally leads to the use of Random Access Memory (RAM) instead of Content Addressable Memory (CAM) needed for broadcast. HeDGE is distinguished from prior approaches in part because it dynamically inserts forwarding instructions. Although these additional instructions degrade performance by an

• Type: Conference
• Year: 2009
• Where: HIPEAC
• Authors: Suriya Subramanian, Kathryn S. McKinley
• Keywords: Dynamic In-flight Instructions, HeDGE Wakeup Logic, HIPEAC 2009, System Software, Wakeup Logic