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DATE
2004
IEEE

Hierarchical Modeling and Simulation of Large Analog Circuits

10 years 3 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction by deriving the exact or approximate admittances in rational form in the reduced circuit matrix and deriving the circuit characteristics for very large linear analog and interconnect circuits. We characterize some theoretical results regarding the conditions on the generations of canceling terms during the general hierarchical circuit analysis and propose an explicit de-cancellation scheme to remove canceling terms based on a new hierarchical symbolic analysis framework. The resulting algorithm can be used for modeling and simulation of linear analog and interconnect circuits in both frequency and time domain.
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DATE
Authors Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
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