A High-level Interconnect Power Model for Design Space Exploration

— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications between logic modules, clock distribution networks, and power supply rails. The main purpose of our model is to set forward a simple methodology to efficiently obtain first-order estimates of interconnect power in early stages of the design process. Hence, the objective is to provide designers and/or high-level design automation tools with a way to quickly explore the design space and weed out architectures whose interconnect power requirements do not meet the allocated power budget. In addition to switching power, which includes inter-wire coupling, our model also considers power due to vias and repeaters. Our experimental results show that in comparison to an accurate low-level model, the error in our method in estimating total switching power is only 6% (while the speedup is three-to-four orders of magnitud...

• Type: Conference
• Year: 2003
• Where: ICCAD
• Authors: Pallav Gupta, Lin Zhong, Niraj K. Jha
• Keywords: Hardware, ICCAD 2003, Interconnect Power Requirements, Length Distribution Model, Total Switching Power