High Level Synthesis from Sim-nML Processor Models

The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Several software generation tools have been developed that take ISA specifications in Sim-nML as input. In this paper we present a tool Sim-HS that implements high level behavioral and structural synthesis of processors from their ISA specifications in Sim-nML. Behavioral SimHS transforms Sim-nML specifications of a processor to the corresponding behavioral Verilog model that is suitable for fast functional simulation. Structural Sim-HS generates structural synthesizable Verilog processor model from its Sim-nML specifications.

• Type: Conference
• Year: 2003
• Where: VLSID
• Authors: Souvik Basu, Rajat Moona
• Keywords: Behavioral Verilog Model, Computer Architecture, ISA Specifications, Structural Synthesizable Verilog, VLSID 2003