A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

Abstract—This paper presents a high-speed digital feedforward Delta-Sigma Modulator which relaxes timing requirement for the Dynamic Element Matching (DEM) algorithm. By making the main Digital to Analog Converter (DAC) process a small part of the input signal, the distortion from the DAC is suppressed. The proposed method allows eliminating the DEM circuitry in the critical data path for high-speed applications, thus achieving high-resolution without augmenting considerable silicon area. Analysis and simulation results verify the effectiveness of the proposed method.

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Sunwoo Kwon, Un-Ku Moon
• Keywords: Considerable Silicon Area, Critical Data Path, DEM Circuitry, ISCAS 2007