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2008

High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform

11 years 11 months ago
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D DWT with computation time as low as 2 12 can be easily achieved for an image with controlled increase of hardware cost. Compared with recently published 2-D DWT architectures with computation time of 2 3 and 2 2 3, the proposed designs can also save a large amount of multipliers and/or storage elements. It can also be used to implement those 2-D DWT traditionally suitable for lifting or flipping-based designs, such as (9,7) and (6,10) DWT. The throughput rate can be improved by a factor of 4 by the proposed approach, but the hardware cost increases by a factor of around 3. Furthermore, the proposed designs have very simple control signals, regular structures and 100% hardware utilization for continuous images.
Chao Cheng, Keshab K. Parhi
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TSP
Authors Chao Cheng, Keshab K. Parhi
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