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2008
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A high speed word level finite field multiplier using reordered normal basis

11 years 6 months ago
A high speed word level finite field multiplier using reordered normal basis
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered normal basis is presented. Proposed architecture has a very regular structure which makes it suitable for VLSI implementation. Architectural complexity comparison shows that the new architecture has smaller critical path delay compared to other word level multipliers available in open literature at the cost of having moderately higher area complexity. The new architecture out performs all other similar proposals considering the product of area and delay as a measure of performance.
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISCAS
Authors Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi
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