High-throughput decoder for low-density parity-check code

— We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18µm, 6 metal-layer CMOS technology. The chip size is 36mm2 .

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto
• Keywords: ASPDAC 2006, Chip Size, LDPC Decoder Chip, Practical Chip Size