Hybrid BIST Using an Incrementally Guided LFSR

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Hybrid BIST Using an Incrementally Guided LFSR
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture [1] is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LFSR so that it can embed patterns that detect the random-pattern-resistant faults in the pseudo-random sequence. Compared with external testing, the proposed approach achieves dramatic reductions in tester storage requirements while using very simple on-chip hardware. Results indicate that the proposed approach provides very attractive tradeoffs between test length and tester storage requirements.
C. V. Krishna, Nur A. Touba
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where DFT
Authors C. V. Krishna, Nur A. Touba
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