Hyper-Systolic Matrix Multiplication

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A novel parallel algorithm for matrix multiplication is presented. It is based on a 1-D hyper-systolic processor abstraction. The procedure can be implemented on all types of parallel systems.

Thomas Lippert, Klaus Schilling

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1-D Hyper-systolic Processor | Matrix Multiplication | Parallel Systems | PDPTA 1996 | PDPTA 2007 |

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Added	02 Nov 2010
Updated	02 Nov 2010
Type	Conference
Year	1996
Where	PDPTA
Authors	Thomas Lippert, Klaus Schilling

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Hyper-Systolic Matrix Multiplication

1-D Hyper-systolic Processor | Matrix Multiplication | Parallel Systems | PDPTA 1996 | PDPTA 2007 |

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